JPH088138Y2 - 半導体の実装構造 - Google Patents
半導体の実装構造Info
- Publication number
- JPH088138Y2 JPH088138Y2 JP1987176324U JP17632487U JPH088138Y2 JP H088138 Y2 JPH088138 Y2 JP H088138Y2 JP 1987176324 U JP1987176324 U JP 1987176324U JP 17632487 U JP17632487 U JP 17632487U JP H088138 Y2 JPH088138 Y2 JP H088138Y2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor element
- semiconductor
- mounting structure
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 39
- 239000011347 resin Substances 0.000 claims description 14
- 229920005989 resin Polymers 0.000 claims description 14
- 238000007789 sealing Methods 0.000 claims description 8
- 230000000630 rising effect Effects 0.000 claims description 7
- 238000005538 encapsulation Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Credit Cards Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987176324U JPH088138Y2 (ja) | 1987-11-20 | 1987-11-20 | 半導体の実装構造 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987176324U JPH088138Y2 (ja) | 1987-11-20 | 1987-11-20 | 半導体の実装構造 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0180473U JPH0180473U (en]) | 1989-05-30 |
JPH088138Y2 true JPH088138Y2 (ja) | 1996-03-06 |
Family
ID=31468065
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987176324U Expired - Lifetime JPH088138Y2 (ja) | 1987-11-20 | 1987-11-20 | 半導体の実装構造 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH088138Y2 (en]) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS596839U (ja) * | 1982-07-07 | 1984-01-17 | 日本電気株式会社 | 半導体装置 |
JPS6232548U (en]) * | 1985-08-14 | 1987-02-26 | ||
JPS62182560U (en]) * | 1986-05-12 | 1987-11-19 |
-
1987
- 1987-11-20 JP JP1987176324U patent/JPH088138Y2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0180473U (en]) | 1989-05-30 |
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